D A T A S H E E T
memory, enabling the system to read the boot-up firm-
RESET#: Hardware Reset Pin
ware from the Flash memory.
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
system drives the RESET# pin to V for at least a pe-
IL
riod of t , the device immediately terminates any
RP
operation in progress, tristates all data output pins,
and ignores all read/write attempts for the duration of
the RESET# pulse. The device also resets the internal
state machine to reading array data. The operation
that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence,
to ensure data integrity.
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET#
is asserted when a program or erase operation is not
executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
(not during Embed-
READY
after
RH
the RESET# pin returns to V .
IH
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
0.3 V, the device
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
SS
). If RESET# is
CC4
held at V but not within V
rent will be greater.
0.3 V, the standby cur-
IL
SS
Output Disable Mode
When the OE# input is at V , output from the device is
disabled. The output pins are placed in the high im-
pedance state.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
IH
22358B7 May 5, 2006
Am29LV160D
11
AMD [ AMD ]
