D A T A S H E E T
sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
and I read specifications apply. Refer to “Write Op-
CC
eration Status” for more information, and to “AC
IL
IH
Characteristics” for timing diagrams.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V ± 0.3 V.
(Note that this is a more restricted voltage range than
CC
V
.) If CE# and RESET# are held at V , but not
IH
IH
within V
± 0.3 V, the device will be in the standby
CC
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
mode, but the standby current will be greater. The de-
vice requires standard access time (t ) for read
access when the device is in either of these standby
modes, before it is ready to read data.
CE
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” and “Au-
toselect Command Sequence” sections for more
information.
In the DC Characteristics table, I
sents the standby current specification.
and I
repre-
CC4
CC3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
+ 30 ns. The automatic sleep mode is
ACC
I
in the DC Characteristics table represents the ac-
CC2
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
the system. I
represents the automatic sleep mode current
specification.
in the DC Characteristics table
CC4
Program and Erase Operation Status
During an erase or program operation, the system
may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings
10
Am29LV160D
May 5, 2006 22358B7
AMD [ AMD ]
