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L160DB90VC 参数 Datasheet PDF下载

L160DB90VC图片预览
型号: L160DB90VC
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位(2M ×8位/ 1的M× 16位) CMOS 3.0伏只引导扇区闪存 [16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存
文件页数/大小: 52 页 / 1792 K
品牌: AMD [ AMD ]
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D A T A S H E E T  
DEVICE BUS OPERATIONS  
This section describes the requirements and use of  
the device bus operations, which are initiated through  
the internal command register. The command register  
itself does not occupy any addressable memory loca-  
tion. The register is composed of latches that store the  
commands, along with the address and data informa-  
tion needed to execute the command. The contents of  
the register serve as inputs to the internal state ma-  
chine. The state machine outputs dictate the function  
of the device. Table 1 lists the device bus operations,  
the inputs and control levels they require, and the re-  
sulting output. The following subsections describe  
each of these operations in further detail.  
Table 1. Am29LV160D Device Bus Operations  
DQ8–DQ15  
BYTE#  
= V  
Addresses  
(Note 1)  
DQ0– BYTE#  
Operation  
CE# OE# WE# RESET#  
DQ7  
= V  
IH  
IL  
Read  
Write  
L
L
L
H
L
H
H
A
D
D
DQ8–DQ14 = High-Z,  
DQ15 = A-1  
IN  
OUT  
OUT  
H
A
D
D
IN  
IN  
IN  
V
0.3 V  
±
V
0.3 V  
±
CC  
CC  
Standby  
X
X
X
High-Z High-Z  
High-Z  
Output Disable  
Reset  
L
H
X
H
X
H
L
X
X
High-Z High-Z  
High-Z High-Z  
High-Z  
High-Z  
X
Sector Address,  
A6 = L, A1 = H,  
A0 = L  
Sector Protect (Note 2)  
L
H
L
V
D
X
X
X
ID  
IN  
Sector Address,  
A6 = H, A1 = H,  
A0 = L  
Sector Unprotect (Note 2)  
L
H
X
L
V
V
D
D
X
ID  
ID  
IN  
IN  
Temporary Sector  
Unprotect  
X
X
A
D
High-Z  
IN  
IN  
Legend:  
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out  
IL  
IH  
ID  
IN  
IN  
OUT  
Notes:  
1. Addresses are A19:A0 in word mode (BYTE# = V ), A19:A-1 in byte mode (BYTE# = V ).  
IH  
IL  
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector  
Protection/Unprotection” section.  
The internal state machine is set for reading array  
Word/Byte Configuration  
data upon device power-up, or after a hardware re-  
The BYTE# pin controls whether the device data I/O  
set. This ensures that no spurious alteration of the  
pins DQ15–DQ0 operate in the byte or word configura-  
memory content occurs during the power transition.  
tion. If the BYTE# pin is set at logic ‘1’, the device is in  
No command is necessary in this mode to obtain  
word configuration, DQ15–DQ0 are active and con-  
array data. Standard microprocessor read cycles that  
trolled by CE# and OE#.  
assert valid addresses on the device address inputs  
If the BYTE# pin is set at logic ‘0’, the device is in byte  
configuration, and only data I/O pins DQ0–DQ7 are  
active and controlled by CE# and OE#. The data I/O  
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is  
used as an input for the LSB (A-1) address function.  
produce valid data on the device data outputs. The  
device remains enabled for read access until the  
command register contents are altered.  
See “Reading Array Data” for more information. Refer  
to the AC Read Operations table for timing specifica-  
tions and to Figure 13 for the timing diagram. I  
the DC Characteristics table represents the active cur-  
rent specification for reading array data.  
in  
CC1  
Requirements for Reading Array Data  
To read array data from the outputs, the system must  
drive the CE# and OE# pins to V . CE# is the power  
IL  
control and selects the device. OE# is the output control  
and gates array data to the output pins. WE# should re-  
Writing Commands/Command Sequences  
To write a command or command sequence (which in-  
cludes programming data to the device and erasing  
main at V . The BYTE# pin determines whether the  
IH  
device outputs array data in words or bytes.  
22358B7 May 5, 2006  
Am29LV160D  
9