Table 40. Parallel Port Cycles1
33-MHz
External Bus
Symbol
Parameter Description
Notes
Unit
Min
2
Max
20
2
t1
t2
PPDWE delay from IOW
PPOEN delay from IOW
STRB delay from IOW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
20
t3
2
20
3
t4
SLCTIN, AFDT valid from IOW
SD setup to IOW
2
20
t5
50
50
t6
SD hold from IOW
4
4
t7
BUSY asserted from IOW asserted
IOW deasserted from BUSY deasserted
IOW pulse width
300
t8
100
450
1000
20
20
2
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
SLCTIN, AFDT recovery
5
5
2
3
DBUFOE setup to IOW
DBUFOE hold from IOW
PPDWE delay from IOR
20
20
SLCTIN, AFDT valid from IOR
SD setup to IOR deasserted
SD hold from IOR
2
20
0
4
4
BUSY asserted from IOR asserted
IOR deasserted from BUSY deasserted
IOR pulse width
300
100
450
0
5
5
DBUFOE, DBUFRDL setup to IOR
DBUFOE, DBUFRDL hold from IOR
10
Notes:
1. The signal names used in Figure 48 and Figure 49 are the PC/AT Compatible and Bidirectional mode signal names.
2. During EPP mode and Bidirectional mode, PPDWE acts as the parallel port chip select and is asserted for both reads and
writes. For PC/AT Compatible mode, PPDWE will be asserted only for parallel port write cycles.
3. These timings are only valid for EPP mode.
4. BUSY is asserted to add wait states to the parallel port access.
5. DBUFOE and DBUFRDL may be required when using the VESA local bus interface or a x32 DRAM interface.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
113
AMD [ AMD ]
