Table 39. VESA Local Bus Cycles
33-MHz
External Bus
Symbol
Parameter Description
Unit
Min
27
14
14
3
Max
t1
t2
t3
t4
t5
VL_LCLK period
ns
ns
ns
ns
ns
VL_LCLK pulse High
VL_LCLK pulse Low
VL_ADS delay from VL_LCLK
18
SA25–SA2, VL_BE3–VL_BE0, VL_M/IO, VL_W/R, VL_D/C delay from
VL_LCLK
3
18
t6
t7
VL_BLAST valid from VL_LCLK
3
18
20
ns
ns
VL_LDEV valid from SA25–SA2, VL_BE3–VL_BE0, VL_M/IO, VL_W/R,
VL_D/C
t81
t9
VL_LDEV setup to VL_LCLK
15
12
0
ns
ns
ns
ns
ns
ns
ns
VL_LRDY, VL_BRDY setup to VL_LCLK
VL_LRDY, VL_BRDY (VL-Bus target is driver) hold from VL_LCLK
VL_LRDY (VL-Bus target is driver) three stated from VL_LCLK
Read data setup to VL_LCLK
t10
t11
t12
t13
t14
0
5
0
3
Read data hold from VL_CLK
Write data delay from VL_CLK
18
Notes:
1. LDEV is checked on the following rising edge of the CPU clock (not shown, up to 100 MHz) from the assertion of ADS. ADS
can assert a minimum of 20 ns after address change.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
111
AMD [ AMD ]
