P R E L I M I N A R Y
PIN DESCRIPTION
Analog
Digital
SDATA
Serial Data
Input/Output
PDO
0-3
Pseudo AUI Data Output
Input
Single-ended receiver.Data input from the IMR2 device.
Transfers command and status data between the
QuIET device and the IMR2 chip.
DIR
Direction
Input
PDI
0-3
Pseudo AUI Data Input
Output
Selects the direction of command data and status data
transfer between the QuIET device and the IMR2 chip.
Single-ended output driver. Data output to the
IMR2 device.
RST
Reset
Input, Active Low
PCI
0-3
Pseudo AUI Collision Input
Output
Resets the internal registers of the QuIET device.
Single-ended output driver. Collision output to the
IMR2 device.
CLK
Clock
Input
TXD+ ,TXD-
0-3
0-3
Transmit Data
Output
20-Mhz clock signal. The clock signal should be the
same one that is used by all IMR2 devices connected
to the QuIET chip.
10BASE-T port differential drivers.
RXD+ , RXD-
TEST
Input, Active High
0-3
Receive Data
Input
0-3
Reserved for factory use only. This pin does have an
internal pull-down, but should be tied LOW for
normal operation.
10BASE-T port differential receivers.
REXT
DV
External Resistor
Input
DD
Digital Power
Power Pin
REXT must be tied to AV
through a 13 kΩ ±1%
DD
These pins supply +5-V power to the digital portion of
the device. These pins should be decoupled and kept
separate from the analog power plane.
resistor.This provides the current reference for all inter-
nal analog functions.
AV
DD
Analog Power
Power Pin
DV
SS
Digital Ground
Ground Pin
These pins supply +5-V power to the analog portion of
the device. These pins should be decoupled and kept
separate from the digital power plane.
These pins provide the ground reference for the digital
portions of the QuIET circuitry.
AV
SS
Note: All digital I/O pins are CMOS and TTL compatible.
Analog Ground
Ground Pin
These pins provide the ground reference for the analog
portions of the QuIET circuitry.
Am79C988A
7
AMD [ AMD ]
