4
RXD(3:0)
RX_DV
RX_ER
Receive Signals
RX_CLK
CRS
Network Status Signals
COL
4
Am79C978
TXD(3:0)
TX_EN
Transmit Signals
TX_CLK
MDC
Management Port Signals
MDIO
22206B-4
Figure 1. Media Independent Interface
MII Receive Interface
MII Network Status Interface
The MII also provides signals that are consistent and
necessary for IEEE 802.3 and IEEE 802.3u operation.
These signals are CRS (Carrier Sense) and COL (Col-
lision Sense). Carrier Sense is used to detect non-idle
activity on the network. Collision Sense is used to indi-
cate that simultaneous transmission has occurred in a
half-duplex network.
The MII receive clock is also generated by the external
PHY and is sent to the Am79C978 controller on the
RX_CLK input pin. The clock will be the same fre-
quency as the TX_CLK but will be out of phase and can
run at 25 MHz or 2.5 MHz, depending on the speed of
the network to which the external PHY is attached.
The RX_CLK is a continuous clock during the reception
of the frame, but can be stopped for up to two RX_CLK
periods at the beginning and the end of frames, so that
the external PHY can sync up to the network data traffic
necessary to recover the receive clock. During this
time, the external PHY may switch to the TX_CLK to
maintain a stable clock on the receive interface. The
Am79C978 controller will handle this situation with no
loss of data. The data is a nibble-wide (4 bits) data
path, RXD(3:0), from the external PHY to the
Am79C978 controller and is synchronous to the rising
edge of RX_CLK.
MII Management Interface
The MII provides a two-wire management interface so
that the Am79C978 controller can control and receive
status from external PHY devices.
The Network Port Manager copies the PHYAD after the
Am79C978 controller reads the EEPROM and uses it
to communicate with the external PHY. (Refer also to
the BCR49 description). The PHY address must be
programmed into the EEPROM prior to starting the
Am79C978 controller. This is necessary so that the in-
ternal management controller can work autonomously
from the software driver and can always know where to
access the external PHY. The Am79C978 controller is
unique by offering direct hardware support of the exter-
nal PHY device without software support. The PHY ad-
dress of 1Fh is reserved and should not be used. To
access the internal or external PHYs, the software
driver must have knowledge of the PHY’s address be-
fore attempting to address it.
The receive process starts when RX_DV is asserted.
RX_DV will remain asserted until the end of the receive
frame. The Am79C978 controller requires CRS (Car-
rier Sense) to toggle in between frames in order to re-
ceive them properly. Errors in the currently received
frame are signaled across the MII by the RX_ER pin.
RX_ER can be used to signal special conditions out of
band when RX_DV is not asserted. Two defined out-of-
band conditions for this are the 100BASE-TX signaling
of bad Start of Frame Delimiter and the 100BASE-T4
indication of illegal code group before the receiver has
synched to the incoming data. The Am79C978 control-
ler will not respond to these conditions. All out of band
conditions are currently treated as NULL events.
The MII Management Interface uses the MII Control,
Address, and Data registers (BCR32, 33, 34) to control
and communicate to the external PHYs. The
Am79C978 controller generates MII management
frames to the external PHY through the MDIO pin syn-
chronous to the rising edge of the Management Data
Clock (MDC) based on a combination of writes and
reads to these registers.
34
Am79C978
AMD [ AMD ]
