TX_EN
TDO
Transmit Enable
Output
Test Data Out
Output
TX_EN indicates when the Am79C978 device is pre-
senting valid transmit nibbles on the MII TXD[3:0] bus.
While TX_EN is asserted, the Am79C978 device gen-
erates TXD[3:0] and TX_ER on TX_CLK rising edges.
TX_EN is asserted with the first nibble of preamble and
remains asserted throughout the duration of the packet
until it is deasserted prior to the first TX_CLK following
the final nibble of the frame. TX_EN transitions are syn-
chronous to TX_CLK.
TDO is the test data output path from the Am79C978
controller. The pin is tri-stated when the JTAG port is in-
active.
TMS
Test Mode Select
Input
A serial input bit stream on the TMS pin is used to de-
fine the specific boundary scan test to be executed.
The pin has an internal pull-up resistor.
MDC
Ethernet Network Interfaces
TX±
Management Data Clock
Output
MDC is the non-continuous clock output that provides
a timing reference for bits on the MDIO pin. During MII
management port operations, MDC runs at a nominal
frequency of 2.5 MHz. When no management opera-
tions are in progress, MDC is driven LOW.
Serial Transmit Data
Output
These pins carry the transmit output data and are con-
nected to the transmit side of the magnetics module.
RX±
If the MII port is not selected, the MDC pin may be left
floating.
Serial Receive Data
Input
These pins accept the receive input data from the mag-
netics module.
MDIO
Management Data Input/Output
Output
Input/
IREF
Internal Current Reference
Input
MDIO is a bidirectional MII management port data pin.
MDIO is an output during the header portion of the
management frame transfers and during the data por-
tion of write operations. MDIO is an input during the
data portion of read operations.
This pin serves as a current reference for the inte-
grated 1/10 PHY. It must be connected to VSS through
a 12100-Ω resistor (1%).
PHY_RST
If a PHY is attached to the MII port via a MII physical
connector then the MDIO pin should be externally
pulled down to Vss with a 10 kΩ ±5% resistor. If a PHY
is directly attached to the MII pins then the MDIO pin
should be externally pulled up to Vcc with a 10 kΩ ±5%
resistor.
PHY Reset
Output
This output is used to reset the external PHY. This out-
put eliminates the need for a fanout buffer on the PCI
reset (RST) signal, provided polarity control for the
specific PHY used, and prevents the resetting of the
PHY when the PG input is LOW. The output polarity is
determined by the RST_POL (CRS116, bit0).
IEEE 1149.1 (1990) Test Access Port
Interface
HomePNA PHY Network Interface
HRTXRXP/HRTXRXN
TCK
Test Clock
Input
Serial Receive Data
Input/Output
TCK is the clock input for the boundary scan test mode
operation. It can operate at a frequency of up to 10
MHz. TCK has an internal pull-up resistor.
These pins accept the receive input data from the mag-
netics module and carry the transmit output data. A
102-Ω resistor should be placed between these pins.
TDI
Clock Interface
XCLK/XTAL
Test Data In
Input
TDI is the test data input path to the Am79C978 con-
troller. The pin has an internal pull-up resistor.
External Clock/Crystal Select
Input
When HIGH, an external 60-MHz clock source is se-
lected bypassing the crystal circuit and clock trippler.
When LOW, a 20-MHz crystal is used instead. The fol-
lowing table illustrates how this pin works.
Am79C978
31
AMD [ AMD ]
