The Auto-Poll’s frequency of generating MII manage-
ment frames can be adjusted by setting of the APDW
bits (BCR32, bits 10-8). The delay can be adjusted
from 0 MDC periods to 2048 MDC periods. Auto-Poll
by default will only read the MII Status register of the
currently active PHY.
Slave Bus Interface Unit
The slave Bus Interface Unit (BIU) controls all ac-
cesses to the PCI configuration space, the Control and
Status Registers (CSR), the Bus Configuration Regis-
ters (BCR), and the Address PROM (APROM) loca-
tions. Table 5 shows the response of the Am79C978
controller to each of the PCI commands in slave mode.
Network Port Manager
If the PHY is active, the Network Port Manager will re-
quest status from the selected PHY by generating MII
management frames. These frames will be sent
roughly every 900 ms. These frames are necessary so
that the Network Port Manager can monitor the current
active link and can notify the software if the current link
goes down.
Table 5. Slave Commands
C[3:0]
0000
0001
0010
Command
Use
Interrupt
Not used
Not used
Acknowledge
Special Cycle
10BASE-T PHY
Read of CSR, BCR, APROM,
and Reset registers
I/O Read
I/O Write
The 10BASE-T transceiver incorporates the physical
layer function, including both clock recovery (ENDEC)
and transceiver function. Data transmission over the
10BASE-T medium requires an integrated 10BASE-T
MAU. The transceiver will meet the electrical require-
ments for 10BASE-T as specified in IEEE 802.3i. The
transmit signal is filtered on the transceiver to reduce
harmonic content per IEEE 802.3i. Since filtering is
performed in silicon, external filtering modules are not
needed. The 10BASE-T PHY transceiver receives 10
Mbps data from the MAC across the internal MII at 2.5
million nibbles per second (parallel), or 10 million bits
per second (serial) for 10BASE-T. It then Manchester
encodes the data before transmission to the network.
Write to CSR, BCR, and
APROM
0011
0100
0101
Reserved
Reserved
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers. Read of the
Expansion Bus
0110
Memory Read
Memory mapped I/O write of
CSR, BCR, and APROM
0111
Memory Write
1000
1001
Reserved
Reserved
The RX+ pins are differential twisted-pair receivers.
When properly terminated, each receiver will meet the
electrical requirements for 10BASE-T as specified in
IEEE 802.3i. Each receiver has internal filtering and
does not require external filter modules. The
10BASE-T PHY transceiver receives a Manchester
coded 10BASE-T data stream from the medium. It then
recovers the clock and decodes the data. The data
stream is presented at the internal MII interface in par-
allel format.
Configuration
Read
Read of the Configuration
Space
1010
1011
1100
1101
1110
1111
Configuration
Write
Write to the Configuration
Space
Memory Read
Multiple
Aliased to Memory Read
Not used
Dual Address
Cycle
PCI and JTAG Configuration Information
Memory Read
Line
Aliased to Memory Read
Aliased to Memory Write
The PCI device ID and software configuration informa-
tion is as follows in Table 3 and Table 4.
Memory Write
Invalidate
Table 3. PCI Device ID
Slave Configuration Transfers
Vendor ID
Device ID
Rev ID (offset 0x08)
The host can access the PCI configuration space with
a configuration read or write command. The
Am79C978 controller will assert DEVSEL during the
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
select the DWord location in the configuration space.
The Am79C978 controller ignores AD[10:8], because it
1022
2001
51
Table 4. PCI Software Configuration
CSR89
CSR88
JTAG
00001262h
00006003h
1262 6003h
36
Am79C978
AMD [ AMD ]
