Next Receive Buffer Address Upper 129
CSR24
Base Address of Receive Ring Lower 129
CSR25
Base Address of Receive Ring Upper 129
CSR26
Next Receive Descriptor Address Lower 129
CSR27
Next Receive Descriptor Address Upper 130
CSR28
Current Receive Status 132
CSR42
Current Transmit Byte Count 132
CSR43
Current Transmit Status 132
CSR44
Next Receive Byte Count 132
CSR45
Next Receive Status 132
CSR46
Transmit Poll Time Counter 132
CSR47
Transmit Polling Interval 133
CSR48
Receive Poll Time Counter 133
CSR49
Receive Polling Interval 133
CSR5
Extended Control and Interrupt 1 119
CSR58
Software Style 134
CSR6
RX/TX Descriptor Table Length 122
CSR60
Current Receive Descriptor Address Lower
130
CSR29
Current Receive Descriptor Address Upper
130
CSR3
Interrupt Masks and Deferral Control 115
CSR30
Base Address of Transmit Ring Lower 130
CSR31
Base Address of Transmit Ring Upper 130
CSR32
Next Transmit Descriptor Address Lower 130
CSR33
Next Transmit Descriptor Address Upper 130
CSR34
Previous Transmit Descriptor Address Lower
136
Current Transmit Descriptor Address Lower
131
CSR35
CSR61
Previous Transmit Descriptor Address Upper
135, 136
Current Transmit Descriptor Address Upper
131
CSR36
Next Next Receive Descriptor Address Lower
131
CSR37
CSR62
Previous Transmit Byte Count 136
CSR63
Previous Transmit Status 136
CSR64
Next Transmit Buffer Address Lower 136
CSR65
Next Transmit Buffer Address Upper 136
CSR66
Next Transmit Byte Count 137
CSR67
Next Transmit Status 137
CSR7
Extended Control and Interrupt 2 122
CSR72
Receive Ring Counter 137
CSR74
Transmit Ring Counter 137
CSR76
Receive Ring Length 137
Next Next Receive Descriptor Address 131
Next Next Receive Descriptor Address Upper
131
CSR38
Next Next Transmit Descriptor Address Low-
er 131
CSR39
Next Next Transmit Descriptor Address Upper
131
CSR4
Test and Features Control 118
CSR40
Current Receive Byte Count 131
CSR41
4
Am79C978
AMD [ AMD ]
