LED1 Status 149
Crystal Oscillator In 32
BCR50-BCR55
Crystal Oscillator Out 32
Reserved Locations 178
BCR6
CSR0
Controller Status and Control Register 112
LED2 Status 151
CSR1
BCR7
Initialization Block Address 0 115
LED3 Status 153
CSR10
BCR9
Logical Address Filter 2 125
Full-Duplex Control 155
Blanking Interval Speed Settings 79
BLOCK DIAGRAM 4
Block Diagram Low Latency Receive Configura-
tion 83
CSR100
Bus Timeout 141
CSR11
Logical Address Filter 3 126
CSR112
Block Diagram No SRAM Configuration 82
Board Interface 28
Missed Frame Count 142
CSR114
Boundary Scan Circuit 91
Boundary Scan Register 91
BSR Mode Of Operation 91
Buffer Management 60
Buffer Management Unit 3, 59
Buffer Size Tuning 7
Receive Collision Count 142
CSR116
OnNow Power Mode Register 142
CSR12
Physical Address Register 0 126
CSR122
Burst FIFO DMA Transfers 57
Burst Write Transfer 46
Bus Acquisition 42, 43
Bus Command and Byte Enables 26
Bus Configuration Registers 145, 212, 217
Bus Configuration Registers (BCRs) 145
Bus Grant 26
Advanced Feature Control 143
CSR124
Test Register 1 143
CSR125
MAC Enhanced Configuration Control 144
CSR13
Physical Address Register 1 126
Bus Master DMA Transfers 43
Bus Request 27
CSR14
Physical Address Register 2 126
by Driver Type 24
CSR15
C
Mode 127
CLK 26
CSR16
CLK Waveform for 3.3 V Signaling 230
CLK Waveform for 5 V Signaling 230
CLK_FAC Values 166
Clock 26
Initialization Block Address Lower 128
CSR17
Initialization Block Address Upper 128
CSR18
Clock Interface 31
Current Receive Buffer Address Lower 128
Clock Timing 222, 225
COL 30
CSR19
Current Receive Buffer Address Upper 128
Collision 30
CSR2
Collision Detect Function 99
Collision Handling 68
CONNECTION DIAGRAM (144 TQFP) 16
CONNECTION DIAGRAM (160 PQFP) 17
Contents 5
Initialization Block Address 1 115
CSR20
Current Transmit Buffer Address Lower 129
CSR21
Current Transmit Buffer Address Upper 129
Control and Status Registers 112, 208, 215
CRS 30
Crystal 32
CSR22
Next Receive Buffer Address Lower 129
CSR23
Am79C978
3
AMD [ AMD ]
