SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)
External Clock (XTAL) Timing Specifications
Clock Timing
No.
1
Symbol
tPER
Parameter Description
Min
Max
Unit
ns
Cycle time
49.995
50.005
2
tPWH
Cycle high time
Clock low time
0.4* Tcycle
0.4*Tcycle
0.6*Tcycle
0.6*Tcycle
ns
3
tPWL
ns
External Clock (Oscillator) Timing Specification
Clock Timing
No.
1
Symbol
tPER
Parameter Description
Min
Max
Unit
ns
Cycle time
16.665
16.669
2
tPWH
Cycle high time
Clock low time
0.4* Tcycle
0.4*Tcycle
0.6*Tcycle
0.6*Tcycle
ns
3
tPWL
ns
1
2
3
XCLK
22206B-55
Figure 52. Clock Timing
PMD Interface
PECL
No.
160
161
Symbol
Parameter Description
Test Conditions
PECL Load
PECL Load
PECL Load
--
Min
0.5
0.5
--
Max
3
Unit
ns
tR (Note 1) TX+, TX- Rise Time
tF (Note 1) TX+, TX- Fall Time
3
ns
162 tSK (Note 1) TX+ to TX- skew
+200
--
ps
163
164
tS
tH
SDI setup time to XCLK high
SDI hold time to XCLK high
7
ns
--
5
--
ns
Note:
1. Not included in the production test.
161
160
80%
20%
TX+,TX–
TX+
TX–
22206B-56
162
Figure 53. PMD Interface Timing (PECL)
Am79C978
225
AMD [ AMD ]
