SWITCHING CHARACTERISTICS: BUS INTERFACE
Parameter
Symbol
Clock Timing
FCLK
Parameter Name
CLK Frequency
Test Condition
Min
Max
Unit
MHz
0
33
_
@ 1.5 V for 5 V signaling
@ 0.4 VDD for 3.3 V signaling
@ 2.0 V for 5 V signaling
@ 0.4 VDD for 3.3 signaling
@ 0.8 V for 5 V signaling
@ 0.3 VDD for 3.3 V signaling
over 2 V p-p for 5 V signaling
over 0.4 VDD for 3.3 V signaling
(Note 1)
tCYC
tHIGH
tLOW
CLK Period
30
ns
ns
ns
CLK High Time
CLK Low Time
12
12
tFALL
CLK Fall Time
CLK Rise Time
1
1
4
4
V/ns
V/ns
over 2 V p-p for 5 V signaling
over 0.4 VDD for 3.3 V signaling
(Note 1)
tRISE
Output and Float Delay Timing
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY,STOP, DEVSEL, PERR,
SERR
Valid Delay
tVAL
2
11
12
ns
tVAL (REQ)
tON
REQ Valid Delay
2
2
ns
ns
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, DEVSEL Active
Delay
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, DEVSEL Float
Delay
tOFF
28
ns
Setup and Hold Timing
AD[31:00], C/BE[3:0], PAR, FRAME,
tSU
IRDY, TRDY, STOP, DEVSEL, IDSEL
Setup Time
7
0
ns
ns
AD[31:00], C/BE[3:0], PAR, FRAME,
IRDY, TRDY, STOP, DEVSEL, IDSEL
Hold Time
tH
tSU (GNT)
tH (GNT)
GNT Setup Time
GNT Hold Time
10
0
ns
ns
222
Am79C978
AMD [ AMD ]
