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AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ AMD ]
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register when there is receive ac-  
tivity on the network.  
S_RESET or by setting the STOP  
bit.  
This bit is always read/write ac-  
cessible. RCVE is cleared by  
H_RESET and is not affected by  
S_RESET or setting the STOP  
bit.  
1
0
RES  
Reserved locations. Written as  
zeros and read as undefined.  
FDEN  
Full-Duplex Enable. FDEN con-  
trols whether full-duplex opera-  
tion is enabled. When FDEN is  
cleared and the Auto-Negotiation  
is disabled, full-duplex operation  
is not enabled and the  
Am79C978 controller will always  
operate in half-duplex mode.  
When FDEN is set, the  
Am79C978 controller will operate  
in full-duplex mode. Do not set  
this bit when Auto-Negotiation  
is enabled.  
1
0
SPEED  
COLE  
Speed. When this bit is set to 1,  
the device is operating in HIGH  
speed mode.  
Collision Status Enable. When  
this bit is set, a value of 1 is  
passed to the LEDOUT bit in this  
register when there is collision  
activity on the network.  
This bit is always read/write ac-  
cessible. COLE is cleared by  
H_RESET and is not affected by  
S_RESET or setting the STOP  
bit.  
This bit is always read/write ac-  
cessible. FDEN is reset to 0 by  
H_RESET, and is unaffected by  
S_RESET and the STOP bit.  
BCR9: Full-Duplex Control  
BCR16: I/O Base Address Lower  
Note: Bits 15-0 in this register are programmable  
through the EEPROM.  
Bit  
Name  
Description  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
Bit  
Name  
Description  
31-3 RES  
Reserved locations. Written as  
zeros and read as undefined.  
15-5 IOBASEL  
Reserved  
locations.  
After  
H_RESET, the value of these bits  
will be undefined. The settings of  
these bits will have no effect on  
any Am79C978 controller func-  
tion.  
2
FDRPAD  
Full-Duplex Runt Packet Accept  
Disable. When FDRPAD is set to  
1 and full-duplex mode is en-  
abled, the Am79C978 controller  
will only receive frames that meet  
the minimum Ethernet frame  
length of 64 bytes. Receive DMA  
will not start until at least 64 bytes  
or a complete frame have been  
received. By default, FDRPAD is  
cleared to 0. The Am79C978 con-  
troller will accept any length  
frame and receive DMA will start  
according to the programming of  
the receive FIFO watermark.  
Note that there should not be any  
runt packets in a full-duplex net-  
work, since the main cause for  
runt packets is a network collision  
and there are no collisions in a  
full-duplex network.  
These bits are always read/write  
accessible. IOBASEL is not af-  
fected by S_RESET or STOP.  
4-0  
RES  
Reserved locations. Written as  
zeros, read as undefined.  
BCR17: I/O Base Address Upper  
Bit  
Name  
Description  
31-16 RES  
Reserved locations. Written as  
zeros and read as undefined.  
15-0 IOBASEU  
Reserved  
locations.  
After  
H_RESET, the value in this regis-  
ter will be undefined. The settings  
of this register will have no effect  
on any Am79C978 controller  
function.  
This bit is always read/write ac-  
cessible. FDRPAD is cleared by  
H_RESET and is not affected by  
Am79C978  
155