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P R E L I M I N A R Y
the media is considered busy and the MAC should defer
to the existing message. This function is implemented in
hardware in the TAI Unit.
2. The 80188 firmware must perform a write to the
80188 internal UMCS register and set the wait states
to 0 and set the READY control to “also use external
RDY” (i.e., set R2,R1,R0 to 000b). No other value
should be written to these bits. Note that the value
that will eventually be written to the BIU MIR9
register will cause the Am79C930 internal SRDY
signal to be asserted for the proper number of cycles
and will cause the 80188 to experience the
proper delay for the Flash memory device in the
Am79C930-based system.
Additionally, each station is required to implement a Net
Allocation Vector (NAV) in order to determine when the
medium is expected to be busy. The NAV is updated as
Request-to-Send (RTS), Send (CTS), and DATA
frames arrive at the station. RTS, CTS, and DATA
frames include a field that indicates the expected length
of the RTS-CTS-DATA-ACK exchange. The MAC uses
the value in this field to update the NAV and then defers
from initiating transmissions until the NAV has counted
down to zero. If any portion of the RTS-CTS-DATA-ACK
exchange is missing, then a MAC timer will timeout and
the NAV is reset to zero at that time. By refraining from
transmission while the NAV is non-zero, the MAC is
practicing collision avoidance.
3. The 80188 firmware must perform a write to the
Am79C930 internal MIR8 register and set the Flash-
WAIT bits to a value that is appropriate for the Flash
memory timing, given the Am79C930 CLKIN pin fre-
quency and the particular speed-grade of the Flash
memory used in the design.
NAV values may be maintained through use of one of
the 80188 timers. If there is no backoff in progress when
the NAV counter value times out, the firmware will initi-
ate transmission of a frame.
4. The 80188 firmware must perform a write to the
Am79C930 internal MIR9 register and set the
SRAMWAIT bits to a value that is appropriate for the
SRAM memory timing, given the Am79C930 CLKIN
pin frequency and the particular speed-grade of the
SRAM memory used in the design.
Initialization — Am79C930 device initialization is per-
formed by asserting the Am79C930 RESET input for
more than 14 clocks. Following the release of the
RESET signal, the Am79C930 device’s embedded
80188 core will exit the reset state. The embedded
80188 will then proceed with instruction fetching and
execution from memory location FFFF0h. The first fetch
will occur within 13 CLKIN clocks (= 6 and 1/2 80188
CPU clock cycles) of the release of the 80188 reset. The
80188 address FFFF0h will map to a Flash memory lo-
cation, sincetheUMCSregisterofthe80188corewillbe
set to FFF8h following reset. This UMCS value will en-
sure that the initial 80188 address fetch will cause an as-
sertion of the UCS signal, which will cause the memory
interface bus logic to select the Flash memory device.
80188 firmware must modify the value of the UMCS reg-
ister after the first few execution cycles in order to make
more than 1K of the Flash memory available to the
80188 core.
SRAM Memory Management — The 80188 core
accesses the SRAM memory by asserting its Lower
Chip Select (80188 LCS). (Actually, SRAM space is se-
lected whenever the 80188 memory access does not
activate the UCS signal. The internal Upper Chip Select
(UCS) signal is routed into the Bus Interface Unit, since
the 80188 core and the Bus Interface Unit must share
the memory interface bus. When UCS is not activated
for an 80188 transfer, the BIU unit assumes that SRAM
accesses are desired. Therefore, during 80188 ac-
cesses for which UCS is not asserted, SCE will be as-
serted, except for a section of lower memory space that
is redirected toward the TAI section of the Am79C930
device.) The SCE signal may be attached to the CE in-
put of an SRAM memory device external to the
Am79C930 device. Up to 128K of SRAM may be ad-
dressed by the 80188 core (with the exception that 64
bytes of SRAM space is mapped into internal
Am79C930 registers of the BIU and TAI.)
The 80188 firmware should make no access to MIR reg-
isters or to TAI registers (TIR and TCR) until the follow-
ing steps have been completed. Note that these steps
MUST be performed in the order given:
An alternative mapping scheme allows some portion of
the Flash memory to be mapped into a portion of LCS
space. (Normally, Flash memory is mappedonly toUCS
space.) Therefore, depending upon the mapping
scheme that is chosen, LCS may either access SRAM
plus BIU plus TAI space, orLCS may access a portion of
SRAM plus BIU plus TAI space plus a portion of Flash
memory space. For mapping details, see the section on
MAC Firmware Resources.
1. The 80188 firmware must perform a write to the
80188 internal LMCS register and set the wait states
to 0 and set the READY control to “also use external
RDY” (i.e., set R2,R1,R0 to 000b). No other value
should be written to these bits. Note that the value
that will eventually be written to the BIU MIR8
register will cause the Am79C930 internal SRDY
signal to be asserted for the proper number of cycles
and will cause the 80188 to experience the proper
delay for the SRAM memory device in the
Am79C930-based system.
Address values are delivered from the 80188 core to the
SRAM through the BIU and then to the Memory Address
Bus (signals MA[16:0]). AD [7:0] 80188 address signals
are latched inside of the BIU to allow system interface
46
Am79C930
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