P R E L I M I N A R Y
Device Bus Operations
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
command register itself does not occupy any
addressable memory location. The register is
composed of latches that store the commands,
along with the address and data information
needed to execute the command. The contents
of the register serve as inputs to the internal
state machine. The state machine outputs
dictate the function of the device. Table 1 lists
the device bus operations, the inputs and
control levels they require, and the resulting
output. The following subsections describe each
of these operations in further detail.
Table 1. Am29LV800D Device Bus Operations
DQ8–DQ15
BYTE#
BYTE
#
OE WE RESET
Addresses
(Note 1)
DQ0–
Operation
CE#
#
#
H
L
#
H
H
DQ7 = V
= V
IH
IL
Read
Write
L
L
L
A
D
D
OUT
DQ8–DQ14 = High-
Z, DQ15 = A-1
IN
OUT
H
A
D
D
IN
IN
IN
V
0.3 V
V
CC
0.3 V
CC
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
V
D
X
X
X
ID
IN
Sector Address,
A6 = H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
V
D
D
X
ID
ID
IN
IN
Temporary Sector Unprotect
X
X
A
D
High-Z
IN
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
ID
IN
IN
OUT
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V ), A18:A-1 in byte mode (BYTE# = V ).
IH
IL
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
the “Sector Protection/Unprotection” section.
BYTE# pin determines whether the device
outputs array data in words or bytes.
Word/Byte Configuration
The BYTE# pin controls whether the device data
I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic ‘1’,
the device is in word configuration, DQ15–DQ0
are active and controlled by CE# and OE#.
The internal state machine is set for reading
array data upon device power-up, or after a
hardware reset. This ensures that no spurious
alteration of the memory content occurs during
the power transition. No command is necessary
in this mode to obtain array data. Standard
microprocessor read cycles that assert valid
addresses on the device address inputs produce
valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
If the BYTE# pin is set at logic ‘0’, the device is
in byte configuration, and only data I/O pins
DQ0–DQ7 are active and controlled by CE# and
OE#. The data I/O pins DQ8–DQ14 are
tri-stated, and the DQ15 pin is used as an input
for the LSB (A-1) address function.
Requirements for Reading Array Data
See “Reading Array Data” for more information.
Refer to the AC Read Operations table for timing
specifications and to Figure 1 for the timing dia-
gram. ICC1 in the DC Characteristics table repre-
sents the active current specification for reading
array data.
To read array data from the outputs, the system
must drive the CE# and OE# pins to VIL. CE# is
the power control and selects the device. OE# is
the output control and gates array data to the
output pins. WE# should remain at VIH. The
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Am29LV800D
Am29LV800D_00_A4_E January 21, 2005
AMD [ AMD ]
