D A T A S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
100,
110,
120,
JEDEC
tAVAV
Std.
tWC
tAS
Description
90R
100R
110R
120R Unit
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
90
100
110
120
ns
ns
tAVWL
0
15
45
0
Address Setup Time to OE# low during toggle bit
polling
tASO
tAH
Min
Min
Min
ns
ns
ns
tWLAX
Address Hold Time
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
45
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Typ
0
0
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
sec
ns
µs
ns
CE# Hold Time
tWP
Write Pulse Width
35
30
240
7.5
15
tWPH
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Per Byte
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word
Per Byte
6.25
12.5
60
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
tWHWH1
tWHWH1
Per Word
Byte
Single Word/Byte Program
Operation (Note 2, 5)
Typ
Typ
Word
60
Byte
54
Accelerated Single Word/Byte
Programming Operation (Note 2, 5)
Word
54
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Min
0.5
250
50
tVHH
tVCS
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
WE# to RY/BY#
tBUSY
90
100
110
120
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words (or 1–32 bytes) programmed.
4. Effective write buffer specification is based upon a 16-word (or 32-byte) write buffer operation.
5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.
44
Am29LV320MT/B
May 16, 2003
AMD [ AMD ]
