欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM29LV017D-120EC 参数 Datasheet PDF下载

AM29LV017D-120EC图片预览
型号: AM29LV017D-120EC
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位(2M ×8位) CMOS 3.0伏只统一部门快闪记忆体 [16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 48 页 / 952 K
品牌: AMD [ AMD ]
 浏览型号AM29LV017D-120EC的Datasheet PDF文件第23页浏览型号AM29LV017D-120EC的Datasheet PDF文件第24页浏览型号AM29LV017D-120EC的Datasheet PDF文件第25页浏览型号AM29LV017D-120EC的Datasheet PDF文件第26页浏览型号AM29LV017D-120EC的Datasheet PDF文件第28页浏览型号AM29LV017D-120EC的Datasheet PDF文件第29页浏览型号AM29LV017D-120EC的Datasheet PDF文件第30页浏览型号AM29LV017D-120EC的Datasheet PDF文件第31页  
tional sectors are selected for erasure, the entire time-  
out also applies after each additional sector erase com-  
mand. When the time-out is complete, DQ3 switches  
from “0” to “1.If the time between additional sector  
erase commands from the system can be assumed to  
be less than 50 µs, the system need not monitor DQ3.  
See also the “Sector Erase Command Sequence” sec-  
tion.  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions DQ5 produces a “1.This is a failure  
condition that indicates the program or erase cycle was  
not successfully completed.  
The DQ5 failure condition may appear if the system  
tries to program a “1” to a location that is previously pro-  
grammed to “0.Only an erase operation can change  
a “0” back to a “1.Under this condition, the device  
halts the operation, and when the operation has ex-  
ceeded the timing limits, DQ5 produces a “1.”  
After the sector erase command sequence is written,  
the system should read the status on DQ7 (Data# Poll-  
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-  
cepted the command sequence, and then read DQ3. If  
DQ3 is “1”, the internally controlled erase cycle has be-  
gun; all further commands (other than Erase Suspend)  
are ignored until the erase operation is complete. If  
DQ3 is “0”, the device will accept additional sector  
erase commands. To ensure the command has been  
accepted, the system software should check the status  
of DQ3 prior to and following each subsequent sector  
erase command. If DQ3 is high on the second status  
check, the last command might not have been ac-  
cepted. Table 9 shows the outputs for DQ3.  
Under both these conditions, the system must issue the  
reset command to return the device to reading array  
data.  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the  
system may read DQ3 to determine whether or not an  
erase operation has begun. (The sector erase timer  
does not apply to the chip erase command.) If addi-  
Table 9. Write Operation Status  
DQ7  
DQ5  
DQ2  
Operation  
(Note 2)  
DQ6  
(Note 1)  
DQ3  
N/A  
1
(Note 2)  
RY/BY#  
Embedded Program Algorithm  
Embedded Erase Algorithm  
DQ7#  
0
Toggle  
Toggle  
0
0
No toggle  
Toggle  
0
0
Standard  
Mode  
Reading within Erase  
Suspended Sector  
1
No toggle  
0
N/A  
Toggle  
1
Erase  
Suspend Reading within Non-Erase  
Data  
Data  
Data  
0
Data  
N/A  
Data  
N/A  
1
0
Mode  
Suspended Sector  
Erase-Suspend-Program  
DQ7#  
Toggle  
Notes:  
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.  
See “DQ5: Exceeded Timing Limits” for more information.  
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
Am29LV017D  
29  
 复制成功!