Low V Write Inhibit
Logical Inhibit
CC
To avoid initiation of a write cycle during V power-up
Writing is inhibited by holding any one of OE = V ,
IL
CC
and power-down, the Am29F040 locks out write cycles
CE = V or WE = V . To initiate a write cycle CE and
IH IH
for V
< V
(see DC Characteristics section for
WE must be a logical zero while OE is a logical one.
CC
LKO
voltages). When V < V
disabled, all internal program/erase circuits are
disabled, and the device resets to the read mode. The
, the command register is
CC
LKO
Power-Up Write Inhibit
Power-up of the device with WE = CE = V and
IL
Am29F040 ignores all writes until V > V
.The user
OE = V will not accept commands on the rising edge
CC
LKO
IH
must ensure that the control pins are in the correct logic
state when V > V to prevent unintentional writes.
of WE. The internal state machine is automatically
reset to the read mode on power-up.
CC
LKO
Write Pulse “Glitch” Protection
Sector Protect
Noise pulses of less than 5 ns (typical) on OE, CE or
WE will not initiate a write cycle.
Sectors of the Am29F040 may be hardware protected
using programming equipment at the users factory.The
protection circuitry will disable both program and erase
functions for the protected sector(s). Requests to pro-
gram or erase a protected sector will be ignored by the
device.
Am29F040
13
AMD [ AMD ]
