#
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
lowing discussion, the WE pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the WE signal.
#
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
#
#
Am28F256 is designed to support either WE or CE
controlled writes. During a system write cycle, ad-
#
#
dresses are latched on the falling edge of WE or CE
whichever occurs last. Data is latched on the rising edge
#
#
of WE or CE whichever occurs first. To simplify the fol-
BLOCK DIAGRAM
DQ0–DQ7
V
CC
V
SS
Erase
Voltage
Switch
Input/Output
Buffers
V
PP
To Array
State
WE#
Control
Program
Voltage
Switch
Command
Register
Chip Enable
Output Enable
Logic
CE#
OE#
Data
Latch
Low V
Detector
CC
Y-Gating
Y-Decoder
Program/Erase
Pulse Timer
Address
Latch
262,144
Bit
X-Decoder
A0–A14
Cell Matrix
11560F-1
PRODUCT SELECTOR GUIDE
Family Part Number
Am28F256
-120
Speed Options (V
= 5.0 V 10%)
±
-70
70
70
35
-90
90
90
35
-150
150
150
55
-200
200
200
55
CC
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
120
120
50
2
Am28F256
AMD [ AMD ]
