P R E L I M I N A R Y
t1
t2
t3
t4
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Data
AO15–AO8
Address
Data
AD7–AD0
(Write)
LCS, UCS
MCSx, PCSx
Figure 7. Am188ES Microcontroller—Read and Write with Address Bus Disable In Effect
BUS INTERFACE UNIT
Nonmultiplexed Address Bus
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
peripheral control block. The Am186ES and Am188ES
microcontrollers provide an enhanced bus interface
unit with the following features:
The nonmultiplexed address bus (A19–A0) is valid one-
half CLKOUTA cycle in advance of the address on the
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte-write enable sig-
nals, the A19–A0 bus provides a seamless interface to
SRAM, PSRAM, and Flash EPROM memory systems.
Static Bus Sizing
n A nonmultiplexed address bus
The 80C186 microcontroller provided a 16-bit wide
data bus over its entire address range, memory, and
I/O, but did not allow accesses to an 8-bit wide bus.
The 80C188 microcontroller provided a lower-cost in-
terface by reducing the data bus width to 8 bits, again
over the entire address range. The Am188ES micro-
controller follows the 80C188 microcontroller in provid-
ing an 8-bit data bus to all memory and peripherals.
However, the Am186ES microcontroller differs from
the 80C186 microcontroller in allowing programmabil-
ity for data bus widths through fields in the auxiliary
configuration (AUXCON) register, as shown in Table 6.
n On the Am186ES microcontroller, a static bus-siz-
ing option for 8-bit and 16-bit memory and I/O
n Separate byte write enables for high and low bytes
in the Am186ES microcontroller only
n Pseudo Static RAM (PSRAM) support
The standard 80C186/188 microcontroller multiplexed
address and data bus requires system interface logic
and an external address latch. On the Am186ES and
Am188ES microcontrollers, new byte write enables,
PSRAM control logic, and a new nonmultiplexed ad-
dress bus can reduce design costs by eliminating this
external logic.
The width of the data access should not be modified
while the processor is fetching instructions from the as-
sociated address space.
Am186/188ES and Am186/188ESLV Microcontrollers
41
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