Switching Characteristics over Commercial and Industrial Operating Ranges
Reset and Bus Hold (25 MHz and 33 MHz)
Preliminary
Parameter
Symbol Description
Reset and Bus Hold Timing Requirements
25 MHz
Min
33 MHz
Min
No.
Max
Max
Unit
tCLAV
tCLAZ
tRESIN
tHVCL
5
AD Address Valid Delay
AD Address Float Delay
RES Setup Time
0
0
20
20
0
0
8
8
15
15
ns
ns
ns
ns
15
57
58
10
10
HOLD Setup(a)
Reset and Bus Hold Timing Responses
tCLHAV
tCHCZ
tCHCV
62
63
HLDA Valid Delay
0
20
20
20
0
15
15
15
ns
ns
ns
Command Lines Float Delay
Command Lines Valid Delay (after Float)
64
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
This timing must be met to guarantee recognition at the next clock.
Switching Characteristics over Commercial and Industrial Operating Ranges
Reset and Bus Hold (40 MHz and 50 MHz)
Preliminary
Parameter
Symbol Description
Reset and Bus Hold Timing Requirements
40 MHz
Min
50 MHz
Min
No.
Max
Max
Unit
tCLAV
tCLAZ
tRESIN
tHVCL
5
AD Address Valid Delay
AD Address Float Delay
RES Setup Time
0
0
5
5
12
12
0
0
5
5
10
10
ns
ns
ns
ns
15
57
58
HOLD Setup(a)
Reset and Bus Hold Timing Responses
62
63
HLDA Valid Delay
0
12
12
12
0
10
10
10
ns
ns
ns
tCLHAV
tCHCZ
tCHCV
Command Lines Float Delay
Command Lines Valid Delay (after Float)
64
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
This timing must be met to guarantee recognition at the next clock.
Am186TMER and Am188TMER Microcontrollers Data Sheet
99
AMD [ AMD ]
