Reset Waveforms
X1
57
57
RES
CLKOUTA
Note:
RES must be held Low for 1 ms during power-up to ensure proper device initialization. Activating the PLL will require 1 ms
to achieve a stable clock.
Signals Related to Reset Waveforms
RES
CLKOUTA
BHE/ADEN*,
Divide by Two and Times One Modes
RFSH2/ADEN*,
S6/CLKSEL1* **,
UZI/CLKSEL2**
S1/IMDIS*,
Three-State
and S0/SREN*
AD15–AD0 (186)
AO15–AO8,
Three-State
AD7–AD0 (188)
Times Four Mode
S6/CLKSEL1***,
UZI/CLKSEL2***
Three-State
Notes:
* Because BHE, RFSH2, S6, UZI, S1, and S0 are not driven for 6.5 clocks after reset, their alternate functions can be
asserted with external pulldown resistors.
** In Divide by Two mode and Times One mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 3 clock cycles after
reset negates.
***In Times Four mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 5 clock cycles after reset negates.
100
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
