PLL, 44
reset configuration register, 48
power consumption calculation, 62
power savings, 59
reset waveforms, 100
related signals, 100
revision history, 10
RFSH2/ADEN, 35
RXD/PIO28, 35
power-save mode
clock waveforms, 95
power-save operation, 48
PQFP connection diagram and pinouts
Am186ER, 22
Am188ER, 25
S
PQFP physical dimensions, 105
S0/SREN, 37
PQFP pin assignments
Am186ER
S1/IMDIS, 37
S2, 35
sorted by pin name, 24
sorted by pin number, 23
Am188ER
S6/CLKSEL1/PIO29, 37
SCLK/PIO20, 37
SDATA/PIO21, 37
SDEN0/PIO22, 37
SDEN1/PIO23, 37
sorted by pin name, 27
sorted by pin number, 26
programmable I/O (PIO) pins, 57
programming
serial ports
interrupt control unit, 53
ready and wait-state, 49
DMA transfers, 55
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
software halt cycle waveforms, 91
pseudo static RAM
support, 44
PSRAM
source clock
external, 45
support, 44
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM read cycle waveforms, 80
SRDY/PIO6, 38
SSI, 102
multiple read, 58
multiple write, 58
waveforms, 103
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM refresh cycle waveforms, 86
support, 13
switching characteristics
PSRAM write cycle
waveforms, 83
clock (25 MHz), 92
clock (33 MHz), 93
clock (40 and 50 MHz), 94
commercial, 67
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
industrial, 67
internal RAM show read cycle (25 and 33 MHz), 76
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
read cycle (25 and 33 MHz), 70
R
RAM
interaction with external, 52
RD, 35
read cycle waveforms, 72
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
ready and wait-state programming, 49
refresh control unit, 53
read cycle (40 and 50 MHz), 71
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
related documents, 13
RES, 35
reset
initialization and processor, 48
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
Index-4
Am186™CC Communications Controller Data Sheet
AMD [ AMD ]
