D
H
DC characteristics, 60
HLDA, 32
HOLD, 32
demonstration board products, 13
DEN/PIO5, 31
hotline and world wide web support, 13
description, 1
functional, 40
I
direct memory access, 54
DMA
I/O circuitry, 59
Am186ER maximum transfer rates, 55
asynchronous serial port transfers, 55
channel control registers, 55–56
operation, 55
I/O space, 40
industrial operating ranges, 60
initialization and processor reset, 48
input/output circuitry, 59
priority, 55–56
INT0, 32
transfers through serial port, 56
unit block diagram, 56
INT1/SELECT, 32
documentation
INT2/INTA0/PIO31, 33
See customer support.
INT3/INTA1/IRQ, 33
DRQ1–DRQ0, 32
DT/R/PIO4, 32
INT4/PIO30, 33
interaction with external RAM, 52
internal memory, 52
internal memory disable, 52
internal RAM show read cycle waveform, 77
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
interrupt acknowledge cycle waveforms, 89
E
emulator and debug modes, 52
internal memory disable, 52
show read enable, 52
external source clock, 45
interrupt control unit, 53
programming, 53
F
features
J
3.3-V operation with 5-V-tolerant I/O, 14
available native development tools, applications, and
system software, 1
junction temperature calculation, 62
enhanced bus interface, 1
L
enhanced functionality, 1, 14
enhanced integrated peripherals, 1
enhanced performance, 14
faster access to memory and clock input modes, 1
integrated RAM, 14
memory integration, 1
software-compatible, 1
x86 software compatibility, 14
LCS/ONCE0, 33
literature
See customer support.
logic diagram
ARDY and SRDY synchronization, 49
low memory chip select, 51
low-voltage operation, 57
low-voltage standard, 59
four-pin interface, 57
functional description, 40
G
GND, 32
Index-2
Am186™CC Communications Controller Data Sheet
AMD [ AMD ]
