P R E L I M I N A R Y
Adder Control
20-bit Adder/Subtractor
Logic
Timer Request
DRQ1
20
Request
Selection
Logic
DRQ0
Transfer Counter Ch. 1
Destination Address Ch. 1
DMA
Control
Logic
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
Interrupt
Request
Channel Control Register 1
Channel Control Register 0
20
16
Internal Address/Data Bus
Figure 10. DMA Unit Block Diagram
DMA Channel Control Registers
DMA Priority
Each DMA control register determines the mode of op-
eration for the particular DMA channel. This register
specifies the following:
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles, except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold
takes priority over an internal DMA cycle.
n The mode of synchronization
n Whether bytes or words are transferred
n If an interrupt is generated after the last transfer
n If DMA activity ceases after a programmed number
of DMA cycles
Because an interrupt request cannot suspend a DMA
operation and the CPU cannot access memory during
a DMA cycle, interrupt latency time suffers during se-
quences of continuous DMA cycles. An NMI request,
however, causes all internal DMA activity to halt. This
allows the CPU to respond quickly to the NMI request.
n The relative priority of the DMA channel with re-
spect to the other DMA channel
n Whether the source address is incremented, decre-
mented, or maintained constant after each transfer
n Whether the source address addresses memory or
I/O space
n Whether the destination address is incremented,
decremented, or maintained constant after trans-
fers
n Whether the destination address addresses mem-
ory or I/O space
Am186/188EM and Am186/188EMLV Microcontrollers
47
AMD [ AMD ]
