P R E L I M I N A R Y
TIMER CONTROL UNIT
DIRECT MEMORY ACCESS (DMA)
There are three 16-bit programmable timers in the
Am186EM and Am188EM microcontrollers. Timer 0
and timer 1 are connected to four external pins (each
one has an input and an output). These two timers can
be used to count or time external events, or to generate
nonrepetitive or variable-duty-cycle waveforms. In ad-
dition, timer 1 can be configured as a watchdog timer
interrupt.
Direct memory access (DMA) permits transfer of data
between memory and peripherals without CPU involve-
ment. The DMA unit in the Am186EM and Am188EM
microcontrollers, shown in Figure 10, provides two
high-speed DMA channels. Data transfers can occur be-
tween memory and I/O spaces (e.g., memory to I/O) or
within the same space (e.g., memory-to-memory or I/O-to-
I/O). In addition, either bytes or words can be transferred
to or from even or odd addresses on the Am186EM micro-
controller. The Am188EM microcontroller does not sup-
port word transfers. Only two bus cycles (a minimum of
eight clocks) are necessary for each data transfer.
The watchdog timer interrupt provides a mechanism for
detecting software crashes or hangs. The TMROUT1
output is internally connected to the watchdog timer in-
terrupt. The TIMER1 count register must then be re-
loaded at intervals less than the TIMER1 max count to
assure the watchdog interrupt is not taken. If the code
crashes or hangs, the TIMER1 countdown will cause a
watchdog interrupt.
Each channel accepts a DMA request from one of
three sources—the channel request pin (DRQ1–
DRQ0), timer 2, or the system software. The channels
can be programmed with different priorities in the event
of a simultaneous DMA request or if there is a need to
interrupt transfers on the other channel.
Timer 2 is not connected to any external pins. It can be
used for real-time coding and time-delay applications.
It can also be used as a prescale to timers 0 and 1 or
as a DMA request source.
DMA Operation
Each channel has six registers in the peripheral control
block that define specific channel operations. The DMA
registers consist of a 20-bit source address (2 regis-
ters), a 20-bit destination address (2 registers), a 16-bit
transfer count register, and a 16-bit control register.
The timers are controlled by eleven 16-bit registers in
the peripheral control block. A timer’s timer-count reg-
ister contains the current value of that timer. The timer-
count register can be read or written with a value at any
time, regardless of whether the timer is running. The
microcontroller increments the value of the timer-count
register each time a timer event occurs.
The DMA transfer count register (DTC) specifies the
number of DMA transfers to be performed. Up to 64K
byte or word transfers can be performed with automatic
termination. The DMA control registers define the
channel operation. All registers can be modified dur-
ing any DMA activity. Any changes made to the DMA
registers are reflected immediately in DMA operation.
Each timer also has a maximum-count register that de-
fines the maximum value the timer will reach. When the
timer reaches the maximum value, it resets to 0 during
the same clock cycle—the value in the maximum-count
register is never stored in the timer-count register.
Also, timers 0 and 1 have a secondary maximum-count
register. Using both the primary and secondary maxi-
mum-count registers lets the timer alternate between
two maximum values.
Table 6. Am186EM Microcontroller Maximum
DMA Transfer Rates
Maximum DMA
Type of Synchronization
Selected
Transfer Rate (Mbyte/s)
40 33 25 20
MHz MHz MHz MHz
If the timer is programmed to use only the primary max-
imum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is
reached. If the timer is programmed to use both of its
maximum-count registers, the output pin indicates
which maximum-count register is currently in control,
thereby creating a waveform. The duty cycle of the
waveform depends on the values in the maximum-
count registers.
Unsynchronized
Source Synch
10
10
8.25 6.25
8.25 6.25
5
5
Destination Synch
(CPU needs bus)
6.6
8
5.5
6.6
4.16
5
3.3
4
Destination Synch
(CPU does not need bus)
Each timer is serviced every fourth clock cycle, so a
timer can operate at a speed of up to one-quarter the
internal clock frequency. A timer can be clocked exter-
nally at this same frequency; however, because of in-
ternal synchronization and pipelining of the timer
circuitry, the timer output may take up to six clock cy-
cles to respond to the clock or gate input.
46
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
