Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
Min
50 MHz
Min
No.
Symbol Description
Max
Max
Unit
General Timing Requirements
tDVCL
tCLDX
1
2
Data in Setup
Data in Hold(b)
5
2
5
2
ns
ns
General Timing Responses
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
5
AD Address Valid Delay
Data Valid Delay
0
0
0
12
12
0
0
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Status Hold Time
9
ALE Active Delay
12
10
tCLCL–5=20
10
11
23
80
81
84
ALE Width
15
tCHLL
tLHAV
tCLCLX
tCLCSL
tLRLL
ALE Inactive Delay
ALE High to Address Valid
LCS Inactive Delay
LCS Active Delay
12
10
7.5
5
0
12
12
0
10
10
0
0
tCLCL + tCLCH –1.25
tCLCL + tCLCH –1
LCS Precharge Pulse Width
Read Cycle Timing Responses
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHDX
tAVRL
tCHAV
24
25
AD Address Float to RD Active
RD Active Delay
0
0
ns
ns
ns
ns
ns
ns
ns
ns
0
10
12
0
35
10
10
2tCLCL–10=40
26
RD Pulse Width
27
RD Inactive Delay
0
0
RD Inactive to ALE High(a)
RD High to Data Hold on AD Bus(b)
A Address Valid to RD Low
CLKOUTA High to A Address Valid
tCLCH–1.25
tCLCH–1
28
59
0
0
2tCLCL–10=40
2tCLCL–10=30
66
68
0
10
0
10
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
Testing is performed with equal loading on referenced pins.
If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Am186TMER and Am188TMER Microcontrollers Data Sheet
79
AMD [ AMD ]
