Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Refresh Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
Min
50 MHz
Min
No.
Symbol Description
Max
Max
Unit
General Timing Responses
tCHLH
tLHLL
tCHLL
9
ALE Active Delay
ALE Width
12
10
ns
ns
ns
tCLCL–5=20
10
11
15
ALE Inactive Delay
12
10
10
10
Read/Write Cycle Timing Responses
tCLRL
tRLRH
tCLRH
tRHLH
tCLCLX
tCLCSL
25
26
27
28
80
81
RD Active Delay
0
0
35
ns
ns
ns
ns
ns
ns
2tCLCL–10=40
RD Pulse Width
RD Inactive Delay
RD Inactive to ALE High(a)
LCS Inactive Delay
LCS Active Delay
0
12
0
10
tCLCH–2
tCLCH–2
0
0
12
12
0
0
10
10
Refresh Timing Cycle Parameters
tCLRFD
tCLRF
tRFCY
tLCRF
79
82
CLKOUTA Low to RFSH Valid
CLKOUTA High to RFSH Invalid
RFSH Cycle Time
0
0
12
12
0
0
10
10
ns
ns
ns
ns
6 x tCLCL
2tCLCL –1.25
6 x tCLCL
2tCLCL –1.25
85
86
LCS Inactive to RFSH Active Delay
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
Testing is performed with equal loading on referenced pins.
Am186TMER and Am188TMER Microcontrollers Data Sheet
85
AMD [ AMD ]
