Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
40 MHz
Min
50 MHz
Min
No.
Symbol Description
Max
Max
Unit
General Timing Responses
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
5
AD Address Valid Delay
Data Valid Delay
0
0
0
12
12
0
0
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Status Hold Time
9
ALE Active Delay
12
10
tCLCL–5=20
10
11
20
23
80
81
84
ALE Width
15
tCHLL
tCVCTV
tLHAV
tCLCLX
tCLCSL
tLRLL
ALE Inactive Delay
Control Active Delay 1(b)
ALE High to Address Valid
LCS Inactive Delay
LCS Active Delay
12
12
10
10
0
0
7.5
5
0
12
12
0
10
10
0
0
tCLCL + tCLCH –1.25
tCLCL + tCLCH –1
LCS Precharge Pulse Width
Write Cycle Timing Responses
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
tAVWL
tCHAV
tAVBL
30
31
Data Hold Time
Control Inactive Delay(b)
0
0
ns
ns
ns
ns
ns
ns
ns
ns
0
12
0
10
2tCLCL–10=40
tCLCH–2
32
WR Pulse Width
35
tCLCH–2
33
WR Inactive to ALE High(a)
Data Hold after WR(a)
tCLCL–10=15
tCLCL+tCHCL–1.25
12
34
tCLCL+tCHCL–1.25
65
A Address Valid to WR Low
CLKOUTA High to A Address Valid
A Address Valid to WHB, WLB Low
68
0
10
18
0
10
15
tCHCL–1.25
tCHCL–1.25
87
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, WR, WHB and WLB signals.
82
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
