Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No. Symbol Description
General Timing Responses
25 MHz
Min
33 MHz
Min
Max
Max Unit
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
5
AD Address Valid Delay
Data Valid Delay
0
0
0
20
20
0
0
0
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Status Hold Time
9
ALE Active Delay
20
15
tCLCL–10=30
tCLCL–10=20
10
11
23
20
80
81
84
ALE Width
tCHLL
tLHAV
tCVCTV
tCLCLX
tCLCSL
tLRLL
ALE Inactive Delay
ALE High to Address Valid
Control Active Delay 1(b)
LCS Inactive Delay
LCS Active Delay
20
15
15
15
0
0
20
20
20
10
0
0
15
15
0
0
tCLCL + tCLCH –3
tCLCL + tCLCH –3
LCS Precharge Pulse Width
Write Cycle Timing Responses
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
tAVWL
30
31
32
33
34
65
Data Hold Time
Control Inactive Delay(b)
0
0
ns
ns
ns
ns
ns
ns
0
20
0
15
2tCLCL–10=70
tCLCH–2
2tCLCL–10=50
tCLCH–2
WR Pulse Width
WR Inactive to ALE High(a)
Data Hold after WR(a)
A Address Valid to WR Low
tCLCL–10=30
tCLCL+tCHCL–3
tCLCL–10=20
tCLCL+tCHCL–3
CLKOUTA High to A
Address Valid
tCHAV
tAVBL
68
0
20
20
0
15
15
ns
ns
A Address Valid to WHB, WLB
Low
87
tCHCL–3
tCHCL–3
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, WR, WHB and WLB signals.
Am186TMER and Am188TMER Microcontrollers Data Sheet
81
AMD [ AMD ]
