P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over Commercial operating ranges
Read Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Requirements
20 MHz
Min
25 MHz
Min
No. Symbol
Max
Max Unit
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold(c)
10
3
10
3
ns
ns
General Timing Responses
3
4
tCHSV
tCLSH
tCLAV
tCLAX
tCHDX
tCHLH
tLHLL
Status Active Delay
Status Inactive Delay
AD Address Valid Delay and BHE
Address Hold
0
0
0
0
0
25
25
25
25
0
0
0
0
0
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
5
6
8
Status Hold Time
9
ALE Active Delay
ALE Width
25
20
10
tCLCL–10=
tCLCL–10=
30
40
11
12
13
tCHLL
tAVLL
tLLAX
ALE Inactive Delay
25
20
ns
ns
ns
AD Address Valid to ALE Low(a)
tCLCHL–2
tCHCL–2
tCLCH–2
tCHCL–2
AD Address Hold from ALE
Inactive(a)
14
15
16
17
tAVCH
tCLAZ
AD Address Valid to Clock High
AD Address Float Delay
0
0
ns
ns
ns
ns
tCLAX=0
0
25
25
tCLAX=0
0
20
20
tCLCSV MCS/PCS Active Delay
tCXCSX MCS/PCS Hold from Command
Inactive(a)
tCLCH–2
tCLCH–2
18
19
20
21
22
23
99
tCHCSX MCS/PCS Inactive Delay
0
0
25
0
0
20
ns
ns
ns
ns
ns
ns
ns
tDXDL
DEN Inactive to DT/R Low(a)
tCVCTV Control Active Delay 1(b)
tCVDEX DEN Inactive Delay
0
25
12
25
0
20
12
20
0
0
tCHCTV Control Active Delay 2(b)
0
0
tLHAV
tPLAL
ALE High to Address Valid
PCS Low to ALE Low
20
15
15
15
28
24
Read Cycle Timing Responses
24
25
26
tAZRL
tCLRL
tRLRH
AD Address Float to RD Active
RD Active Delay
0
0
0
0
ns
ns
ns
25
25
20
20
2tCLCL–15=
85
2tCLCL–15=
65
RD Pulse Width
27
28
29
tCLRH
tRHLH
tRHAV
RD Inactive Delay
RD Inactive to ALE High(a)
0
0
ns
ns
ns
tCLCH–3
tCLCH–3
RD Inactive to AD Address
Active(a)
tCLCL–10=
40
tCLCL–10=
30
41
tDSHLH DS Inactive to ALE High
tCLCH–2=
21
tCLCH–2=
16
59
66
tRHDX
tAVRL
RD High to Data Hold on AD Bus(c)
A Address Valid to RD Low(a)
0
0
ns
ns
tCLCL
+
tCLCL+
t
CHCL–3
t
CHCL–3
67
68
tCHCSV CLKOUTA High to LCS/UCS Valid
0
0
25
25
0
0
20
20
ns
ns
tCHAV
CLKOUTA High to A Address
Valid
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
c
Equal loading on referenced pins.
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
68
Am186/188ES and Am186/188ESLV Microcontrollers
AMD [ AMD ]
