P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Write Cycle (20 MHz and 25 MHz)
Preliminary
Parameter
Description
General Timing Responses
20 MHz
Min
25 MHz
Min
No. Symbol
Max
Max Unit
3
4
tCHSV
tCLSH
tCLAV
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
tLLAX
Status Active Delay
Status Inactive Delay
AD Address Valid Delay and BHE
Address Hold
0
0
0
0
0
0
25
25
25
25
15
0
0
0
0
0
0
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
7
Data Valid Delay
8
Status Hold Time
9
ALE Active Delay
25
20
10
11
12
13
ALE Width
tCLCL–10=40
tCLCL–10=30
ALE Inactive Delay
AD Address Valid to ALE Low(a)
25
20
tCLCH –2
tCHCL–2
tCLCH–2
tCHCL–2
AD Address Hold from ALE
Inactive(a)
14
16
17
tAVCH
AD Address Valid to Clock High
0
0
0
0
ns
ns
ns
tCLCSV MCS/PCS Active Delay
25
25
20
20
tCXCSX MCS/PCS Hold from Command
Inactive(a)
tCLCH–2
tCLCH–2
18
19
20
21
22
23
tCHCSX MCS/PCS Inactive Delay
0
0
0
0
ns
ns
ns
ns
ns
ns
tDXDL
DEN Inactive to DT/R Low(a)
tCVCTV Control Active Delay 1(b)
0
15
25
25
0
20
20
20
tCVDEX DS Inactive Delay
0
0
tCHCTV Control Active Delay 2
0
0
tLHAV
ALE High to Address Valid
20
15
Write Cycle Timing Responses
30
31
32
33
34
35
41
tCLDOX Data Hold Time
tCVCTX Control Inactive Delay(b)
0
0
ns
ns
ns
ns
ns
ns
0
25
0
20
tWLWH WR Pulse Width
2tCLCL–10=90
tCLCH–2
tCLCL–10=40
tCLCH–3
2tCLCL–10=70
tCLCH–2
tCLCL–10=30
tCLCH–3
tWHLH
WR Inactive to ALE High(a)
tWHDX Data Hold after WR(a)
tWHDEX WR Inactive to DEN Inactive(a)
tDSHLH DS Inactive to ALE High
tCLCH–2=
21
tCLCH–2=
16
65
67
68
tAVWL
A Address Valid to WR Low
tCLCL+tCHCL–3
tCLCL+tCHCL–3
ns
ns
ns
tCHCSV CLKOUTA High to LCS/UCS Valid
0
0
25
25
0
0
20
20
tCHAV
tAVBL
CLKOUTA High to A Address
Valid
87
A Address Valid to WHB, WLB
Low
tCHCL–3
35
25
tCHCL–3
0
20
30
ns
ns
98
tDSHDIW DS High to Data Invalid—Write
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
b
Testing is performed with equal loading on referenced pins.
This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
Am186/188ES and Am186/188ESLV Microcontrollers
71
AMD [ AMD ]
