D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Table 16. Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
0.7
14
5
15
Excludes00hprogrammingprior
to erasure (Note 4)
s
Byte Programming Time
150
210
16
µs
µs
s
Word Programming Time
Byte Mode
Word Mode
7
Excludes system level overhead
(Note 5)
5.3
3.7
Chip Programming Time
(Note 3)
11
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further
information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
Table 17. Latchup Characteristics
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
11.0 V
Input voltage with respect to VSS on all I/O pins
–0.5 V
VCC + 0.5 V
+100 mA
V
CC Current
–100 mA
Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.
Table 18. TSOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Table 19. Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
January 23, 2007 27546A6
Am29SL800D
39
AMD [ AMD ]
