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A800DB90PF 参数 Datasheet PDF下载

A800DB90PF图片预览
型号: A800DB90PF
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 1.8伏只超低电压闪存 [8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory]
分类和应用: 闪存
文件页数/大小: 46 页 / 1066 K
品牌: AMD [ AMD ]
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D A T A S H E E T  
for command definitions). In addition, the following  
hardware data protection measures prevent accidental  
erasure or programming, which might otherwise be  
START  
caused by spurious system level signals during V  
CC  
power-up and power-down transitions, or from system  
noise.  
RESET# = VID  
(Note 1)  
Low V  
Write Inhibit  
CC  
When V  
is less than V  
, the device does not  
LKO  
CC  
Perform Erase or  
Program Operations  
accept any write cycles. This protects data during V  
CC  
power-up and power-down. The command register and  
all internal program/erase circuits are disabled, and the  
RESET# = VIH  
device resets. Subsequent writes are ignored until V  
CC  
is greater than V  
. The system must provide the  
LKO  
proper signals to the control pins to prevent uninten-  
tional writes when V is greater than V  
.
CC  
LKO  
Temporary Sector  
Unprotect Completed  
(Note 2)  
Write Pulse “Glitch” Protection  
Noise pulses of less than 5 ns (typical) on OE#, CE# or  
WE# do not initiate a write cycle.  
Logical Inhibit  
Notes:  
Write cycles are inhibited by holding any one of OE# =  
1. All protected sectors unprotected.  
V , CE# = V or WE# = V . To initiate a write cycle,  
IL  
IH  
IH  
2. All previously protected sectors are protected once again.  
CE# and WE# must be a logical zero while OE# is a  
logical one.  
Power-Up Write Inhibit  
Figure 2. Temporary Sector Unprotect Operation  
If WE# = CE# = V and OE# = V during power up, the  
IL  
IH  
Hardware Data Protection  
The command sequence requirement of unlock cycles  
for programming or erasing provides data protection  
against inadvertent writes (refer to Table 5 on page 19  
device does not accept commands on the rising edge  
of WE#. The internal state machine is automatically  
reset to reading array data on power-up.  
After the device accepts an Erase Suspend command,  
the device enters the Erase Suspend mode. The  
system can read array data using the standard read  
timings, except that if it reads at an address within  
erase-suspended sectors, the device outputs status  
data. After completing a programming operation in the  
Erase Suspend mode, the system may once again  
read array data with the same exception. See Erase  
Suspend/Erase Resume Commands‚ on page 17 for  
more information on this mode.  
COMMAND DEFINITIONS  
Writing specific address and data commands or  
sequences into the command register initiates device  
operations. Table 5 on page 19 defines the valid reg-  
ister command sequences. Writing incorrect address  
and data values or writing them in the improper  
sequence may place the device in an unknown state. A  
reset command is then required to return the device to  
reading array data.  
All addresses are latched on the falling edge of WE# or  
CE#, whichever happens later. All data is latched on  
the rising edge of WE# or CE#, whichever happens  
first. Refer to the appropriate timing diagrams in the  
AC Characteristics‚ on page 28 section.  
The system must issue the reset command to re-  
enable the device for reading array data if DQ5 goes  
high, or while in the autoselect mode. See Reset Com-  
mand‚ on page 14.  
See also Requirements for Reading Array Data‚ on  
page 8 for more information. Table 10 on page 28 pro-  
vides the read parameters, and Figure 12, on page 27  
shows the timing diagram.  
Reading Array Data  
The device is automatically set to reading array data  
after device power-up. No commands are required to  
retrieve data. The device is also ready to read array  
data after completing an Embedded Program or  
Embedded Erase algorithm.  
Reset Command  
Writing the reset command to the device resets the  
device to reading array data. Address bits are don’t  
care for this command.  
14  
Am29SL800D  
27546A6 January 23, 2007  
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