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A800DB90PF 参数 Datasheet PDF下载

A800DB90PF图片预览
型号: A800DB90PF
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 1.8伏只超低电压闪存 [8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory]
分类和应用: 闪存
文件页数/大小: 46 页 / 1066 K
品牌: AMD [ AMD ]
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D A T A S H E E T  
Figure 3 illustrates the algorithm for the program oper-  
ation. See Table 13 on page 31 for parameters, and to  
Figure 17, on page 32 for timing diagrams.  
Chip Erase Command Sequence  
Chip erase is a six bus cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algo-  
rithm automatically preprograms and verifies the entire  
memory for an all zero data pattern prior to electrical  
erase. The system is not required to provide any con-  
trols or timings during these operations. Table 5 on  
page 19 shows the address and data requirements for  
the chip erase command sequence.  
START  
Write Program  
Command Sequence  
Data Poll  
from System  
Embedded  
Program  
algorithm  
in progress  
Any commands written to the chip during the  
Embedded Erase algorithm are ignored. Note that a  
hardware reset during the chip erase operation imme-  
diately terminates the operation. The Chip Erase  
command sequence should be reinitiated once the  
device has returned to reading array data, to ensure  
data integrity.  
Verify Data?  
No  
Yes  
The system can determine the status of the erase oper-  
ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write  
Operation Status” for information on these status bits.  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are  
no longer latched.  
No  
Increment Address  
Last Address?  
Yes  
Programming  
Completed  
Figure 4, on page 18 illustrates the algorithm for the  
erase operation. See Table 13 on page 28 for parame-  
ters, and to Figure 10, on page 26 for timing diagrams.  
1. See Table 5 for program command sequence.  
Sector Erase Command Sequence  
Figure 3. Program Operation  
Sector erase is a six bus cycle operation. The sector  
erase command sequence is initiated by writing two  
unlock cycles, followed by a set-up command. Two  
additional unlock write cycles are then followed by the  
address of the sector to be erased, and the sector  
erase command. Table 5 shows the address and data  
requirements for the sector erase command sequence.  
The device does not require the system to preprogram  
the memory prior to erase. The Embedded Erase algo-  
rithm automatically programs and verifies the sector for  
an all zero data pattern prior to electrical erase. The  
system is not required to provide any controls or  
timings during these operations.  
After the command sequence is written, a sector erase  
time-out of 50 µs begins. During the time-out period,  
additional sector addresses and sector erase com-  
mands may be written. Loading the sector erase buffer  
may be done in any sequence, and the number of  
sectors may be from one sector to all sectors. The time  
between these additional cycles must be less than 50  
µs, otherwise the last address and command might not  
be accepted, and erasure may begin. It is recom-  
mended that processor interrupts be disabled during  
16  
Am29SL800D  
27546A6 January 23, 2007  
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