A D V A N C E I N F O R M A T I O N
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
START
caused by spurious system level signals during V
CC
power-up and power-down transitions, or from system
noise.
RESET# = V
ID
Low V
Write Inhibit
CC
When V
is less than V
, the device does not
LKO
CC
Perform Erase or
Program Operations
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
CC
RESET# = V
device resets. Subsequent writes are ignored until V
IH
CC
is greater than V
. The system must provide the
LKO
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Notes:
Logical Inhibit
1. All protected sectors unprotected.
Write cycles are inhibited by holding any one of OE# =
2. All previously protected sectors are protected once
again.
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
CE# and WE# must be a logical zero while OE# is a
logical one.
Figure 2. Temporary Sector Unprotect Operation
Power-Up Write Inhibit
Hardware Data Protection
If WE# = CE# = V and OE# = V during power up, the
IL
IH
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 on page 17
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 on page 17 defines the valid reg-
ister command sequences. Writing incorrect address
and data values or writing them in the improper
sequence resets the device to reading array data.
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in AC
Characteristics, on page 26.
The system must issue the reset command to
re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the Reset
Command section, next.
See also Requirements for Reading Array Data, on
page 8 for more information. The Read Operations
table provides the read parameters, and Figure 13, on
page 26 shows the timing diagram.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
The reset command may be written between the
sequence cycles in an erase command sequence
April 13, 2005 Rev. A Amend. +1
Am29SL400D
13
AMD [ AMD ]
