A D V A N C E I N F O R M A T I O N
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
within a time of t
rithms). The system can read data t
RESET# pin returns to V .
(not during Embedded Algo-
READY
after the
RH
IH
Refer to AC Characteristics, on page 26 for RESET#
parameters and to Figure 14, on page 27 for the timing
diagram.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
Output Disable Mode
time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
When the OE# input is at V , output from the device is
IH
disabled. The output pins are placed in the high imped-
ance state.
Table 2. Am29SL400DT Top Boot Block Sector Address Table
Sector Size Address Range (in hexadecimal)
(Kbytes/
Kwords)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
0
A13
X
A12
X
(x8) Address Range (x16) Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–77FFFh
78000h–79FFFh
7A000h–7BFFFh
7C000h–7FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3BFFFh
3C000h–3CFFFh
3D000h–3DFFFh
3E000h–3FFFFh
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
1
1
1
1
0
0
1
1
1
1
0
1
8/4
1
1
1
1
1
X
16/8
Table 3. Am29SL400DB Bottom Boot Block Sector Address Table
Sector Size
(Kbytes/
Address Range (in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A17
0
A16
0
A15
0
A14
0
A13
0
A12
X
Kwords)
(x8) Address Range (x16) Address Range
16/8
8/4
00000h–03FFFh
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
0
0
0
0
1
0
0
0
0
0
1
1
8/4
0
0
0
1
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0
0
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration”
section for more information.
10
Am29SL400D
Rev. A Amend. +1 April 13, 2005
AMD [ AMD ]
