A D V A N C E I N F O R M A T I O N
Operations, on page 29 for parameters, and to
Figure 17, on page 30 for timing diagrams.
hardware reset during the chip erase operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
START
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, DQ2, or RY/BY#. See Write
Operation Status, on page 18 for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and
addresses are no longer latched.
Write Program
Command Sequence
Figure 4, on page 16 illustrates the algorithm for the
erase operation. See the Erase/Program
Operations, on page 29 for parameters, and to
Figure 18, on page 31 for timing diagrams.
Data Poll
from System
Embedded
Program
algorithm
in progress
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 on page 17 shows the
address and data requirements for the sector erase
command sequence.
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
Programming
Completed
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
Note: See Table 5 on page 17 for program command
sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 on
page 17 shows the address and data requirements for
the chip erase command sequence.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See DQ3: Sector Erase
Timer, on page 20.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
April 13, 2005 Rev. A Amend. +1
Am29SL400D
15
AMD [ AMD ]
