D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std.
Description
Read Cycle Time (Note 1)
Test Setup
-100R
-110
-120
-150
Unit
tAVAV
tRC
Min
100
110
120
150
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Address to Output Delay
Max
100
110
120
150
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
100
35
110
45
120
50
150
65
ns
ns
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
16
16
0
Read
Output Enable
tOEH
Toggle and
Data# Polling
Hold Time (Note 1)
Min
Min
30
0
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11‚ on page 26 and Table 7 on page 26 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
January 23, 2007 Am29SL400C_00_A6
Am29SL400C
27
AMD [ AMD ]
