D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the de-
vice bus operations, which are initiated through the internal
command register. The command register itself does not oc-
cupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the
address and data information needed to execute the com-
mand. The contents of the register serve as inputs to the in-
ternal state machine. The state machine outputs dictate the
function of the device. Table 1 lists the device bus opera-
tions, the inputs and control levels they require, and the re-
sulting output. The following subsections describe each of
these operations in further detail.
Table 1. Am29SL400C Device Bus Operations
DQ8–DQ15
BYTE#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
Operation
CE#
L
OE# WE# RESET#
= VIL
Read
Write
L
H
L
H
H
AIN
AIN
DOUT
DIN
DOUT
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
L
H
VCC
0.2 V
±
VCC ±
0.2 V
Standby
X
X
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Sector Address, A6
= L, A1 = H,
A0 = L
Sector Protect (Note 2)
L
H
L
VID
DIN
X
X
Sector Address, A6
= H, A1 = H,
A0 = L
Sector Unprotect (Note 2)
L
H
X
L
VID
VID
DIN
DIN
X
X
Temporary Sector Unprotect
X
X
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
that no spurious alteration of the memory content occurs
Word/Byte Configuration
during the power transition. No command is necessary in
The BYTE# pin controls whether the device data I/O pins
this mode to obtain array data. Standard microprocessor
DQ15–DQ0 operate in the byte or word configuration. If the
read cycles that assert valid addresses on the device ad-
BYTE# pin is set at logic ‘1’, the device is in word configura-
dress inputs produce valid data on the device data outputs.
tion, DQ15–DQ0 are active and controlled by CE# and OE#.
The device remains enabled for read access until the com-
mand register contents are altered.
If the BYTE# pin is set at logic ‘0’, the device is in byte con-
figuration, and only data I/O pins DQ0–DQ7 are active and
controlled by CE# and OE#. The data I/O pins DQ8–DQ14
are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
See Reading Array Data‚ on page 15 for more information.
Refer to the AC Read Operations table for timing specifica-
tions and to Figure 14‚ on page 28 for the timing diagram.
ICC1 in the DC Characteristics table represents the active
current specification for reading array data.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must drive
the CE# and OE# pins to VIL. CE# is the power control and
selects the device. OE# is the output control and gates array
data to the output pins. WE# should remain at VIH. The
BYTE# pin determines whether the device outputs array
data in words or bytes.
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE# and CE# to VIL, and
OE# to VIH.
For program operations, the BYTE# pin determines whether
the device accepts program data in bytes or words. Refer
to Word/Byte Configuration‚ on page 9 for more information.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
January 23, 2007 Am29SL400C_00_A6
Am29SL400C
9
AMD [ AMD ]
