D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
2
15
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
70
10
12
8
s
Byte Programming Time
Word Programming Time
Accelerated Program Time, Word/Byte
300
360
240
160
120
µs
µs
µs
s
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
20
14
Chip Programming Time
(Note 3)
s
Notes:
1. Typical program and erase times assume the following conditions: 2ꢀ°C, 2.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
ꢀ. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 12, on page 26 for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
11.0 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–0.5 V
VCC + 0.5 V
+100 mA
–100 mA
Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 2ꢀ°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
46
Am29SL160C
21635C5 January 23, 2007
AMD [ AMD ]
