Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
The PCI bus operation registers are mapped as 16
consecutive DWORD registers located at the address
space (I/O or memory) specified by the Base Address
Register 0. These locations are the primary method of
communication between the PCI and Add-On buses.
Data, software-defined commands and command
parameters can be either exchanged through the mail-
boxes, transferred through the FIFO in blocks under
program control, or transferred using the FIFOs under
Bus Master control. Table 1 lists the PCI Bus Opera-
tion Registers.
Table 30. Operation Registers — PCI Bus
Address Offset
00h
Abbreviation
OMB1
OMB2
OMB3
OMB4
IMB1
Register Name
Outgoing Mailbox Register 1
Outgoing Mailbox Register 2
Outgoing Mailbox Register 3
Outgoing Mailbox Register 4
Incoming Mailbox Register 1
Incoming Mailbox Register 2
Incoming Mailbox Register 3
Incoming Mailbox Register 4
FIFO Register port (bidirectional)
Master Write Address Register
Master Write Transfer Count Register
Master Read Address Register
Master Read Transfer Count Register
Mailbox Empty/Full Status
04h
08h
0Ch
10h
14h
IMB2
18h
IMB3
1Ch
IMB4
20h
FIFO
24h
MWAR
MWTC
MRAR
MRTC
MBEF
INTCSR
MCSR
28h
2Ch
30h
34h
38h
Interrupt Control/Status Register
Bus Master Control/Status Register
3Ch
60
DS1527
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