Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
ification. This section describes each of the
configuration space fields—its address, default values,
initialization options, and bit definitions—and also pro-
vides an explanation of its intended usage.
PCI CONFIGURATION REGISTERS
Each PCI bus device contains a unique 256-byte
region called its configuration header space. Portions
of this configuration header are mandatory in order for
a PCI agent to be in full compliance with the PCI spec-
Table 4. Configuration Registers
Configuration Address Offset
00h–01h
Abbreviation
Register Name
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification Register
Class Code Register
Cache Line Size Register
Master Latency Timer
Header Type
VID
DID
02h–03h
04h–05h
06h–07h
08h
PCICMD
PCISTS
RID
09h–0Bh
0Ch
CLCD
CALN
LAT
0Dh
0Eh
HDR
0Fh
BIST
Built-in Self-test
10h–27h
28h–2Fh
30h
BADR0-BADR5
—
Base Address Registers (0-5)
Reserved
EXROM
—
Expansion ROM Base Address
Reserved
34h–3Bh
3Ch
INTLN
INTPIN
MINGNT
MAXLAT
—
Interrupt Line
3Dh
Interrupt Pin
3Eh
Minimum Grant
3Fh
Maximum Latency
Not used
40h–FFh
32
DS1527
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
