Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
groups: Register access, FIFO access, Pass-Thru
mode pins, and general system pins.
ADD-ON BUS INTERFACE SIGNALS
The following sets of signals represent the interface
pins available for the Add-On function. There are four
Register Access Pins
Signal
Type
Description
DQ[31:00]
t/s
Datapath DQ0–DQ31. These pins represent the datapath for the Add-On peripheral’s data bus. They
provide the interface to the controller’s FIFO and other registers. When MODE=V CC, only DQ[15:00]
are used. DQ[31:0] have internal pull-up resistors.
ADR[6:2]
in
Add-On Addresses. These signals are the address lines to select which of the 16 DWORD registers
within the controller is desired for a given read or write cycle, as shown in the table below.
ADR[6:2]
Register Name
Add-On Incoming Mailbox Reg. 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
Add-On Incoming Mailbox Reg. 2
Add-On Incoming Mailbox Reg. 3
Add-On Incoming Mailbox Reg. 4
Add-On Outgoing Mailbox Reg. 1
Add-On Outgoing Mailbox Reg. 2
Add-On Outgoing Mailbox Reg. 3
Add-On Outgoing Mailbox Reg. 4
Add-On FIFO Port
1
0
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
Bus Master Write Address Register
Add-On Pass-Thru Address
Add-On Pass-Thru Data
1
0
Bus Master Read Address Register
Add-On Mailbox Empty/Full Status
Add-On Interrupt Control
1
1
1
1
0
1
1
1
Add-On General Control/Status Register
Bus Master Write Transfer Count
Bus Master Read Transfer Count
1
1
1
BE3# or
ADR1
in
in
Byte Enable 3 (32-bit mode) or ADR1 (16 bit mode). This pin is used in conjunction with the read or
write strobes (RD# or WR#) and the Add-On select signal, SELECT#. As a Byte Enable, it is neces-
sary to have this pin asserted to perform write operations to the register identified by ADR[6:2] bit loca-
tions d24 through d31; for read operations it controls the DQ[31:24] output drive.
BE[2:0]#
Byte Enable 2 through 0. These pins provide for individual byte control during register read or write
operations. BE2# controls activity over DQ[23:DQ16], BE1# controls DQ[15:8], and BE0# controls
DQ[7:0]. During read operations they control the output drive for each of their respective byte lanes;
for write operations they serve as a required enable to perform the modification of each byte lane.
28
DS1527
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
