S5933
32-Bit PCI “MatchMaker”
TRDY#
s/t/s
Target Ready. This signal is sourced by the selected target and indicates the target is able
to complete the current data phase of a bus transaction. For read operation, it indicates that
the target is providing valid data on the AD[31:0] pins. Wait states occur until both
TRDY# and IRDY# are asserted together.
STOP#
LOCK#
IDSEL
DEVSEL#
INTA#
REQ#
s/t/s
in
Stop. The Stop signal is driven by a selected target and conveys a request to the bus master
to stop the current transaction.
Lock. The lock signal provides for the exclusive use of a resource. The S5933 may be
locked by one master at a time. The S5933 cannot lock a target when it is a master.
in
Initialization Device Select. This pin is used as a chip select during configuration read or
write transactions.
s/t/s
o/d
out
in
Device Select. This signal is driven by a target decoding and recognizing its bus address.
This signal informs a bus master whether an agent has decoded a current bus cycle.
Interrupt A. This signal is defined as optional and a level sensitive Host interrupt. The
INTA# is used for any single function device requiring an interrupt capability.
Request. This signal is sourced by an agent wishing to become the bus master. It is a point-
to-point signal and each master has its own REQ#.
GNT#
Grant. The GNT# signal is a dedicated, point-to-point signal provided to each potential
bus master and signifies that access to the bus has been granted.
PERR#
s/t/s
Parity Error. Is used for reporting data parity errors for all bus transactions except for Spe-
cial Cycles. It is driven by the agent receiving data two clock cycles after the parity was
detected as an error. This signal is driven inactive (high) for one clock cycle prior to
returning to the tri-state condition.
SERR#
SCL
o/d
t/s
System Error. Used to report address and data parity errors on Special Cycle commands
and any other error condition having a catastrophic system impact.
Serial Clock. This clock provides timing for transactions on the two-wire serial bus. This
signal is intended to be directly connected to one serial non-volatile RAM. This pin is
shared with the byte-wide interface signal, ERD#.
SDA
t/s
t/s
Serial Data/Address. This bidirectional pin is used to transfer addresses and data to or
from a serial nvRAM. It is an open drain output requiring a 10K external pull-up resistor.
This pin is shared with the byte-wide interface signal, EWR#.
EA[15:0]
External nv Memory Address. These signals connect directly to the external byte wide or
EPROM address pins EA0 through EA15. The PCI interface controller assembles 32-bit
wide accesses through multiple read cycles of the 8-bit device. The address space from
0040h through 007Fh is used to preload and initialize the PCI configuration registers.
Should an external nv memory be used, the minimum size required is 128 bytes and the
maximum is 64K bytes. When a serial memory is connected to the S5933, the pins
EA[7:0] are reconfigured to become hardware Add-On to PCI mailbox register controls
with the EA8 pin as the mailbox load clock. Also, the EA15 signal pin will provide an
indication that the PCI to Add-On FIFO is full (FRF), and the EA14 signal pin will indi-
cate whether the add-On to PCI FIFO is empty (FWE).
ERD#
out
External nv Memory Read Control. This pin is asserted during read operations involving
the external non-volatile memory. Data is transferred into the S5933 during the low to high
transition of ERD#. This pin is shared with the serial external memory interface signal,
SCL.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
8
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
