S5933
32-Bit PCI “MatchMaker”
TIMING DIAGRAMS
Synchronous RDFIFO# Timing
BPCLK
RDFIFO#
DQ[31:0]
1
2
3
4
New Valid
RDEMPTY
FRF
Old Valid
Notes:
1. The data 1 valid time is dependent on where RDFIFO# is asserted in it's window.
2. The data 4 signal is cut short due to the de-assertion of RDFIFO#.
3. The RDEMPTY is an example relative to data 2, if the FIFO went empty on data 2.
Synchronous WRFIFO# Timing
BPCLK
WRFIFO#
1
2
3
DQ[31:0]
New Valid
WRFULL
FWE
Old Valid
Notes:
1. The WRFULL is an example relative to data 2, if data 2 were to fill the FIFO.
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