S5933
32-Bit PCI “MatchMaker”
The optional nvRAM allows the Add-On card manufac-
turer to initialize the S5933 with his specific Vendor ID
and Device ID numbers along with desired S5933 opera-
tion characteristics. The non-volatile memory feature
also provides for the Expansion BIOS and POST code
(power-on-self-test) options on the PCI bus.
Add-On Bus Operation Registers
Address
Incoming Mailbox Register 1 (AIMB1)
Incoming Mailbox Register 2 (AIMB2)
Incoming Mailbox Register 3 (AIMB3)
Incoming Mailbox Register 4 (AIMB4)
Outgoing Mailbox Register 1 (AOMB1)
Outgoing Mailbox Register 2 (AOMB2)
Outgoing Mailbox Register 3 (AOMB3)
Outgoing Mailbox Register 4 (AOMB4)
FIFO Port (AFIFO)
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
58h
5Ch
Mailbox Operation
The Mailbox Registers are divided into two four
DWORD sets. Each set is dedicated to one bus for trans-
ferring data to the other bus. Figure 3 below shows a
block diagram of the mailbox section of the S5933. The
provision of Mailbox Registers provides an easy path for
the transfer of user information (command, status or
parametric data) between the two buses. An empty/full
indication for each Mailbox Register, at the byte level, is
determined by polling a Status Register accessible to
both the PCI and Add-On buses. Providing Mailbox byte
level empty/full indications allows for greater flexibility
in 8-, 16- or 32-bit system interfaces. i.e., transferring a
single byte to an 8-bit Add-On bus without requiring the
assembling or disassembling of 32-bit data.
Bus Master Write Address Register (MWAR)
Pass-Thru Address Register (APTA)
Pass-Thru Data Register (APTD)
Bus Master Read Address Register (MRAR)
Maibox Empty/Full Status Register (AMBEF)
Interrupt Control/Status Register (AINT)
General Control/Status Register (ARCR)
Bus Master Write Transfer Count (MWTC)
Bus Master Read Transfer Count (MRTC)
Table 3
The generation of interrupts from Mailbox Registers is
equivalent with the commonly known 'DOORBELL'
interrupt technique. Bit locations
configured within the S5933’s Oper-
ation Registers select a Mailbox and
Mailbox byte which is to generate an
interrupt when full or touched. A
mailbox interrupt control register is
then used to enable interrupt genera-
tion and to select if the interrupt is to
be generated on the PCI or Add-On
Local bus. PCI Local bus interrupts
may also be generated from direct
hardware interfacing due to a unique
AMCC feature. A dedicated Mail-
box byte of the S5933 is directly
accessible via a set of hardware
device signal pins. A single mailbox
load signal pin latches Add-On bus
data directly into the Mailbox initiat-
ing a PCI bus interrupt if enabled.
The mailbox data may also be read
in a similar manner. This option is
shared with the byte wide non-vola-
tile memory signal pins. The S5933
S5933
PCI MB1
Byte 0
PCI MB2
Byte 0
PCI MB3
Byte 0
PCI MB4
Byte 0
PCI MB1
Byte 1
PCI MB2
Byte 1
PCI MB3
Byte 1
PCI MB4
Byte 1
PCI MB1
Byte 2
PCI MB2
Byte 2
PCI MB3
Byte 2
PCI MB4
Byte 2
PCI MB1
Byte 3
PCI MB2
Byte 3
PCI MB3
Byte 3
PCI MB4
Byte 3
Add MB1
Byte 0
Add MB2
Byte 0
Add MB3
Byte 0
Add MB4
Byte 0
Add MB1
Byte 1
Add MB2
Byte 1
Add MB3
Byte 1
Add MB4
Byte 1
Add MB1
Byte 2
Add MB2
Byte 2
Add MB3
Byte 2
Add MB4
Byte 2
Add MB1
Byte 3
Add MB2
Byte 3
Add MB3
Byte 3
Add MB4
Byte 3
Mailbox Status Register
Figure 3
must use the serial nvRAM option for the direct mailbox option signals to be available or they will be assigned to the
byte wide at power up.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
4
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
