DEVICE SPECIFICATION
S5933
PCI CONTROLLER
4.7 CACHE LINE SIZE REGISTER (CALN)
This register is hardwired to 0. The cache line con-
figuration register is used by the system to define the
cache line size in doubleword (64-bit) increments.
This controller does not use the “Memory Write and
Invalidate” PCI bus cycle commands when operating
in the bus master mode, and therefore does not inter-
nally require this register. When operating in the tar-
get mode, this controller does not have the
connections necessary to “snoop” the PCI bus and
accordingly cannot employ this register in the detec-
tion of burst transfers that cross a line boundary.
Register Name:
Address Offset:
Power-up value:
Boot-load:
Cache Line Size
0Ch
00h, hardwired
not used
Attribute:
Read Only
8 bits
Size:
Figure 4-7. Cache Line Size Register
7
0
00h
Cache Line Size (RO)
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