DEVICE SPECIFICATION
S5933
PCI CONTROLLER
4.8 LATENCY TIMER REGISTER (LAT)
The latency timer register has meaning only when
this controller is used as a bus master and pertains to
the number of PCI bus clocks that this master will be
guaranteed. The nonzero value for this register is
internally decremented after this device has been
granted the bus and has begun to assert FRAME#.
Prior to this latency timer count reaching zero, this
device can ignore the removal of the bus grant and
may continue the use of the bus for data transfers.
Register Name:
Address Offset:
Power-up value:
Boot-load:
Latency Timer
0Dh
00h
External nvRAM offset
04Dh
Attribute:
Size:
Read/Write, bits 7:3;
Read Only bits 2:0
8 bits
Figure 4-8. Latency Timer Register
7
6
5
4
3
2
0
1
0
0
0
Bit
X
X
X
X
X
Value
Latency Timer value (R/W)
# of clocks x 8
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
4-16
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
